1. Field of the Invention
The present invention relates to a substrate, and particularly relates to an array substrate formed by connecting at least a wire and one of a plurality of test shorting bars which share a part.
2. Description of Related Art
A liquid crystal display panel has the advantages of thin thickness, high resolution, low power consumption, and no radiation, and thus has become the mainstream among all displays panels. Additionally, as liquid crystal display panels become widely used, the haggling competition thereof is getting drastic. Hence, how to effectively reduce production costs to increase competitiveness has become the goal of the manufacturers in this field.
Generally speaking, a liquid crystal display panel is mainly formed by an array substrate, a liquid crystal layer, and a color filter substrate. Herein, in order to effectively fabricate the array substrate, a plurality of arrays is usually formed simultaneously on a mother substrate, and array test procedures and repair procedures are timely performed on each array on the mother substrate during the array process, so as to increase the yield rate thereof. After the array process is finished on the mother substrate, a cutting process is performed to the mother substrate to divide the arrays thereon from each other, so as to complete fabricating a plurality of array substrates.
FIG. 1A is a top view illustrating a plurality of array substrates formed on a mother substrate according to a conventional technique; and FIG. 1B is a top view illustrating an array substrate 100 formed after a cutting process is performed on the mother substrate in FIG. 1A. Referring to FIGS. 1A and 1B, a mother substrate 101 comprises a plurality of pixel arrays, wherein each pixel array located in an array substrate predetermined forming region 100. After the cutting process is performed to the mother substrate 101, each array substrate 100 having a display region P1 and a peripheral circuit region P2 adjacent to the display region P1 is formed. The array substrate 100 comprises a pixel array 110, a plurality of test shorting bars 120, and a plurality of repair lines 130. As shown in FIG. 1B, the pixel array 110 is disposed in the display region P1. The test shorting bars 120 and the repair lines 130 are disposed in the peripheral circuit region P2, and the repair lines 130 are electrically connected with the pixel array 110, wherein the aforesaid array test is to test the circuit by the test shorting bars 120. In a preferable embodiment, the mother substrate 101 comprises a plurality of alignment marks 103. The alignment marks 103 are used for precise alignment, so as to prevent deviation from occurring when a lithographic process, an etching process, an assembling process, or other processes requiring the alignment marks 103 for precise alignment are performed on the mother substrate 101.
In conventional technology, the arrays on the mother substrate 101 are usually arranged as dense as possible to increase the utilization of the mother substrate 101, or the distance between the alignment marks 103 and the arrays is shortened as much as possible to reduce production costs. For example, the size of the mother substrate 101 in FIG. 1A is 1300 mm×1100 mm, and 28 array substrates 100 are arranged as a 7×4 rectangle. However, as a consequence, the positions of a portion of the array substrate predetermined forming regions 100 may become too close to the alignment marks 103 or the alignment marks 103 may fall within the array substrate predetermined forming regions 100, which easily cause the machines to fail to catch the alignment marks 103 during the succeeding fabricating processes, such as a lithographic process, an etching process, an assembling process, or other processes requiring the alignment marks 103 for precise alignment, and result in abnormal alignment. Consequently, the fabrication of the array substrates 100 is influenced.
To solve this problem, the conventional technology applies another arrangement of the substrates 100 in the 1300 mm×1100 mm mother substrate 101. For example, FIG. 1C illustrates another arrangement of the substrates 100. This kind of arrangement allows a certain distance to be maintained between the positions of the array substrate predetermined forming regions 100 and the alignment marks, such that the machines can precisely identify the alignment marks 103. However, this 6×4 arrangement of 24 pieces will reduce the production quantity. Additionally, in consideration of other process margins during the fabrication, such as effective film deposition margin, the layout of the predetermined forming region array substrates 100 on the mother substrate 101 is limited. Therefore, one of the purposes of the present invention is to reduce the region of the peripheral circuit region P2 and decrease the overall outline of the array substrate 100, such that the array substrates 100 can be effectively divided to improve the utilization of the mother substrate 101, and further to reduce the costs for producing the liquid crystal display panels.